TDDB Lifetime Reduction From Charging Damage in a 3D Vertical NAND Memory Technology
Author:
Affiliation:
1. NAND Design, Technology and Manufacturing, Intel Corporation, Folsom, CA, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/7298/10566496/10496492.pdf?arnumber=10496492
Reference11 articles.
1. On the impact of the layout of MOSFET test-structures on NBTI-, PBTI- and HCS-lifetime due to PID
2. A comprehensive model forplasma damage enhanced transistor reliability degradation;Weng
3. Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation
4. Fast Wafer Level Reliability Monitoring: Quantification of Plasma-Induced Damage Detected on Productive Hardware
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