Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs-Reference-Cited by-同舟云学术

Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

Published:2023-06 Issue:2 Volume:23 Page:263-268
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Hung Wei-Chieh¹,Jin Fu-Yuan¹,Chang Ting-Chang²^ORCID,Hung Wei-Chun¹^ORCID,Chang Chin-Han³,Chang Kai-Chun¹,Yeh Chien-Hung⁴,Kuo Ting-Tzu¹,Hsu Jui-Tse⁵,Lee Ya-Huan¹,Huang Jen-Wei⁶

Affiliation:

1. Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan

2. Department of Physics, Center of Crystal Research, College of Semiconductor and Advanced Technology Research, National Sun Yat-sen University, Kaohsiung, Taiwan

3. Institute of Electronics Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan

4. Department of Photonics, National Sun Yat-sen University, Kaohsiung, Taiwan

5. Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan

6. Department of Physics, Military Academy, Kaohsiung, Taiwan

Funder

National Sun Yat-sen University Joint Center for High Value Instruments, Center for NanoScience & NanoTechnology Core Facilities Lab;

Taiwan Semiconductor Research Institute

National Science and Technology Council in Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/7298/10145596/10091233.pdf?arnumber=10091233

Reference27 articles.

1. The influence of LOCOS related oxide etch backs on thin oxide leakage in memory devices

2. Microelectronic Applications of Chemical Mechanical Planarization

3. Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation

4. Failure mechanism and improvement on gate oxide failure at the edge of LOCOS

5. Two-dimensional methodology for modeling radiation-induced off-state leakage in CMOS technologies

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device;IEEE Journal of the Electron Devices Society;2024

2. A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device;IET Circuits, Devices & Systems;2023-10-31