A Speed Up Method towards DDR Subsystem Functional Verification in SoC-Reference-Cited by-同舟云学术

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A Speed Up Method towards DDR Subsystem Functional Verification in SoC

Published:2023-10-24 Issue: Volume: Page:1-4
ISSN:
Container-title:2023 IEEE 15th International Conference on ASIC (ASICON)
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Author:

Jiang Yande¹,Chen Na²,Wang Huiquan¹,Zhang Guangda¹,Xia Jun³,Yan Xiaobo³

Affiliation:

1. Defense Innovation Institute,Academy of Military Science,Beijing,China,100071

2. Beijing University of Technology,Beijing Key Laboratory of Traffic Engineering,Beijing,China,100124

3. Hanhu Laboratory,Artificial Intelligence Chip and System Center,Zhejiang,China,314001

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395907/10395930/10396545.pdf?arnumber=10396545

Reference9 articles.

1. Graphene Nanoribbon Based Complementary Logic Gates and Circuits

2. DMA Function Verification Based on UVM Verification Platform

3. A UVM Verification Platform for RISC-V SoC from Module to System Level

4. Functional coverage-driven UVM-based UART IP verification

5. An introduction to assertion-based verification

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