Author:
Mishra Ashish,Sharma Gaurav Kr,Boolchandani D.
Cited by
9 articles.
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1. Comparative Analysis of Phase/Frequency Detector in a Complete PLL System;2023 International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2023-04-29
2. Power Optimal Phase Locked Loop Using 90nm Technology with Five Stage CS-VCO;2022 3rd International Conference on Communication, Computing and Industry 4.0 (C2I4);2022-12-15
3. A 500 kHz to 150 MHz Multi-Output Clock Generator Using Analog PLL and Open-Loop Fractional Divider with 0.13 μm CMOS;Electronics;2022-07-27
4. Adaptive Locking Range of the Software Phase-Locked Loop (SPLL);2022 International Conference on Electrical, Computer and Energy Technologies (ICECET);2022-07-20
5. Effectiveness of Taguchi and ANOVA in design of differential ring oscillator;Analog Integrated Circuits and Signal Processing;2020-06-15