Comparative Analysis of Phase/Frequency Detector in a Complete PLL System
Author:
Affiliation:
1. BITS,EEE Dept.,Pilani,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10150430/10150434/10150478.pdf?arnumber=10150478
Reference18 articles.
1. Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application
2. Design of phase-locked loop based radio frequency synthesizer;yurdakul;Master’s thesis,2019
3. An LVPECL-based Phase-Frequency Detector with 15 ps Dead Zone in 130 nm SiGe BiCMOS
4. A Low-Jitter 300MHz CMOS PLL for Double Data Rate Applications
5. Design of Low Power Delay Locked Loop in 180-nm Digital CMOS Process;ghorbani,2022
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1. Design and implementation of successive approximation register data converter;AIP Conference Proceedings;2024
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