Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio
Author:
Affiliation:
1. Institute of Smart Cities, Public University of Navarra, Pamplona, Spain
2. Dipartimento di Ingegneria Elettrica, Elettronica e Informatica, University of Catania, Catania, Italy
Funder
Agenzia Estatal de Investigaciòn (AEI), Ministerio de Ciencia e Innovaciòn, Spanish Government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9809796/09726705.pdf?arnumber=9726705
Reference27 articles.
1. 0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier
2. Design and implementation of sub 0.5-V OTAs in 0.18-μm CMOS
3. A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain
4. An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers
5. A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers
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1. GBW Optimization in Two-Stage OTAs Operating in Weak Inversion;2023 38th Conference on Design of Circuits and Integrated Systems (DCIS);2023-11-15
2. A Novel Digital OTA Topology With 66-dB DC Gain and 12.3-kHz Bandwidth;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-11
3. Multi-Verse Optimization for Two Stage CMOS Operational Amplifier Circuit Design;2023 4th International Conference on Smart Electronics and Communication (ICOSEC);2023-09-20
4. Design of Low Noise and Micro Power Two-Stage CMOS Operational Amplifier for Cardiovascular Signal Acquisition;2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS);2023-09-01
5. A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair;Journal of Low Power Electronics and Applications;2023-03-28
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