All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator-Reference-Cited by-同舟云学术

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All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator

Published:2014-02 Issue:2 Volume:61 Page:90-94
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Perez-Puigdemont Jordi,Moll Francesc,Calomarde Antonio

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/6746060/06725696.pdf?arnumber=6725696

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Low Phase Noise PLL with Improved Locking Time;Lecture Notes in Electrical Engineering;2024

2. Design of Low Power Adaptive Path Changing Glitch Free Radix-4, Radix-8 Multipliers;2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC);2022-08-17

3. A high-resolution and glitch-free all-digital variable length ring oscillator design on an FPGA;Computers & Electrical Engineering;2019-03

4. A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle;IEEE Journal of Solid-State Circuits;2017-09

5. ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation System;Proceedings of the 26th edition on Great Lakes Symposium on VLSI;2016-05-18

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