All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM-Reference-Cited by-同舟云学术

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All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM

Published:2015-11 Issue:11 Volume:62 Page:1023-1027
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Jung Dong-Hoon,An Young-Jae,Ryu Kyungho,Park Jung-Hyun,Jung Seong-Ook

Funder

Technology Innovation Industrial Program

Ministry of Trade, industry & Energy (MI, Korea)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/7313049/07156093.pdf?arnumber=7156093

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display;Analog Integrated Circuits and Signal Processing;2023-11-10

2. A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range;Electronics;2023-06-16

3. A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction;Electronics;2023-03-17

4. A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection;IEEE Transactions on Circuits and Systems II: Express Briefs;2021

5. Multi-phases all-digital DLL with multi-input and wide-range delay line;International Journal of Electronics;2020-07-20

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