A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction

Author:

Zeng Zhaoquan12ORCID,Zhang Ling12,Gong Lijiao12ORCID,Zhang Ning12

Affiliation:

1. School of Mechanical and Electrical Engineering, Shihezi University, Shihezi 832000, China

2. Xinjiang Production and Construction Corps Key Laboratory of Advanced Energy Storage Materials and Technology, Shihezi University, Shihezi 832000, China

Abstract

This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μm digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication.

Funder

Shihezi University International Science and Technology Cooperation Promotion Project

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

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