Algorithm Level Error Detection in Low Voltage Systolic Array-Reference-Cited by-同舟云学术

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Algorithm Level Error Detection in Low Voltage Systolic Array

Published:2022-02 Issue:2 Volume:69 Page:569-573
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Safarpour Mehdi^ORCID,Inanlou Reza^ORCID,Silven Olli^ORCID

Funder

6G Flagship Research Programme through Academy of Finland

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9695534/09475533.pdf?arnumber=9475533

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Error Checking for Sparse Systolic Tensor Arrays;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

2. A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators;IEEE Access;2024

3. Optimization and analysis of FPGA-based systolic array for matrix multiplication;AIP Conference Proceedings;2024

4. RunSAFER: A Novel Runtime Fault Detection Approach for Systolic Array Accelerators;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06

5. Precision and Performance-Aware Voltage Scaling in DNN Accelerators;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05

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