Error Checking for Sparse Systolic Tensor Arrays-Reference-Cited by-同舟云学术

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Error Checking for Sparse Systolic Tensor Arrays

Published:2024-04-22 Issue: Volume:22 Page:552-556
ISSN:
Container-title:2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)
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Author:

Peltekis Christodoulos¹,Filippas Dionysios¹,Dimitrakopoulos Giorgos¹

Affiliation:

1. Democritus University of Thrace,Electrical and Computer Engineering,Xanthi,Greece

Funder

Siemens

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10595550/10595552/10595917.pdf?arnumber=10595917

Reference29 articles.

1. Sparsity in deep learning: Pruning and growth for efficient inference and training in neural networks;Hoefler;The Journal of Machine Learning Research,2021

2. Rigging the lottery: Making all tickets winners;Evci

3. Accelerating sparse deep neural networks;Mishra,2021

4. Learning N:M fine-grained structured sparse neural networks from scratch;Zhou

5. Why systolic architectures?

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