Reconfigurable Hardware Design Approach for Economic Neural Network

Author:

Khalil Kasem1ORCID,Kumar Ashok2ORCID,Bayoumi Magdy3

Affiliation:

1. Electrical and Computer Engineering Department, University of Mississippi, Oxford, MS, USA

2. Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA, USA

3. Department of Electrical and Computer Engineering, University of Louisiana at Lafayette, Lafayette, LA, USA

Funder

University of Louisiana at Lafayette

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Reference24 articles.

1. DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures

2. Artificial neural networks in hardware;zheng;Learning in Energy-Efficient Neuromorphic Computing Algorithm and Architecture Co-Design,2020

3. A scalable network-on-chip based neural network implementation on FPGAs;bui;Proc IEEE-RIVF Int Conf Comput Commun Technol (RIVF),2019

4. An Efficient Hardware Implementation of Artificial Neural Network based on Stochastic Computing

5. Resource sharing in feed forward neural networks for energy efficiency;zyarah;Proc IEEE 60th Int Midwest Symp Circuits Syst (MWSCAS),2017

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