A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS-Reference-Cited by-同舟云学术

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A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS

Published:2020-05 Issue:5 Volume:67 Page:806-810
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Rehman Sami Ur^ORCID,Khafaji Mohammad Mahdi^ORCID,Ferschischi Ali,Carta Corrado,Ellinger Frank

Funder

German Research Foundation (DFG) through the HAEC A01 Project and 3D-LommID Project

Fast-Spot Project within the BMBF Federal Ministry’s FAST Cluster

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9082708/09037062.pdf?arnumber=9037062

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process;Analog Integrated Circuits and Signal Processing;2023-12-19

2. A Radiation-Hardened Delay-Locked Loop Applied for Multiple Frequency Ranges;Journal of Circuits, Systems and Computers;2022-10-29

3. Analysis and Design of a Delay-Locked Loop with Multiple Radiation-hardened Techniques;Circuits, Systems, and Signal Processing;2022-08-19

4. Charge Pump Using Gain-Boosting and Positive Feedback Techniques in 180-nm Digital CMOS Process;Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials;2022-04-11

5. Low-Power and High-Speed Design of FinFET-Based MCML Delay Element;Proceedings of First International Conference on Computational Electronics for Wireless Communications;2022

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