Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8920/6299017/06247477.pdf?arnumber=6247477
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low Area and Low Power Threshold Implementation Design Technique for AES S-Box;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-03
2. Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells;Sustainable Computing: Informatics and Systems;2019-03
3. A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-11
4. Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications;Australian Journal of Electrical and Electronics Engineering;2018-07-03
5. Design of thermally aware ultra low power clock generator for moderate speed VLSI chip applications;Australian Journal of Electrical and Electronics Engineering;2018-04-03
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