Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,General Computer Science
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1. Analyzing the Performance of 6T SRAM Cell and 64×64 Memory Array at Lower Technology Nodes for Low Power Design;2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS);2023-09-01
2. Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node;Australian Journal of Electrical and Electronics Engineering;2022-04-26
3. Process evaluation in FinFET based 7T SRAM cell;Analog Integrated Circuits and Signal Processing;2021-09-01
4. Certain investigations in achieving low power dissipation for SRAM cell;Microprocessors and Microsystems;2020-09
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