A Fully Serial-In Parallel-Out Digit-Level Finite Field Multiplier in $\mathbb {F}_{2^{m}}$ Using Redundant Representation
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/8091143/07903594.pdf?arnumber=7903594
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Symmetric And Asymmetric Algorithms for Susceptible Harmful in Wireless Sensor Network on FPGA Platform;2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS);2023-03-17
2. Low-Delay FPGA-Based Implementation of Finite Field Multipliers;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-08
3. Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-07
4. Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-01
5. Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm;2018 IEEE 36th International Conference on Computer Design (ICCD);2018-10
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