A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector

Author:

Lee Dongil,Lee Taeho,Kim Young-Ju,Kim Lee-Sup

Funder

Basic Science Research Program

Ministry of Science, ICT and Future Planning

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Analysis of Input Voltage-Output Frequency Relationship in VCOs Using a Linear Time-Varying Model;2024 Tenth International Conference on Communications and Electronics (ICCE);2024-07-31

2. UWB Low RMS Jitter Phase-Locked Loops Using Voltage-Controlled Oscillator;2024 IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition (iWEM);2024-07-10

3. Output Frequency Calculation for VCO Based on Nonlinear State Space Model;2023 IEEE 12th Global Conference on Consumer Electronics (GCCE);2023-10-10

4. High Performance Injection-Locked PLL Architectures: An Overview;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28

5. A Charge Pump Current Mismatch Compensation Design for Sub-Sampling PLL;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-06

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