Analysis of the Flash ADC Bandwidth–Accuracy Tradeoff in Deep-Submicron CMOS Technologies
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8920/4653500/04653511.pdf?arnumber=4653511
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-07
2. A quantitative design methodology for high-speed interpolation/averaging ADCs;Integration;2017-06
3. An 8-bit flash analog-to-digital converter with an array of redundant comparators;Journal of Communications Technology and Electronics;2017-04
4. A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H;Journal of Circuits, Systems and Computers;2013-09
5. Design Matrix Analysis for Capacitive Interpolation Flash ADC;Journal of Low Power Electronics;2011-02-01
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