A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H

Abstract

In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors realizing the ever desired unique NMCML (NMOS-MCML) structure. Using intermediate gray encoding and exponential gains by extra latches greatly removes the bubble/meta-stability error and increases both the speed and the accuracy. Utilizing a differential ladder and some other deliberate arrangements reduces the kickback noise and common mode interferences, minimizes the structure and facilitates fast recovery of overdrive signals. The proposed ADC is simulated by Hspice using 0.18 μm TSMC technology and shows; effective resolution band width (ERBW) larger than 903 MHz that is 1.36 times more than Nyquist frequency (fs/2), 35.17 dB/49.4 dB SNDR/SFDR, 5.53 bits ENOB (rather flat SNDR and ENOB from 50 MHz to 750 MHz), and the low power consumption of 37.77 mW from a 1.2 V supply. These results prove that applying so many effective and novel plans has obtained a unique all N-MCML flash ADC with power-efficiency of 0.61 pJ per conversion step. Both Monte Carlo and corner cases simulations in addition to temperature analysis are performed that prove both intra-die and inter-die robustness of the proposed structure.