Universal Stability Criterion for Type-I Sampling Phase-Locked Loops-Reference-Cited by-同舟云学术

Universal Stability Criterion for Type-I Sampling Phase-Locked Loops

Published:2023-04 Issue:4 Volume:70 Page:1351-1355
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Huang Yunbo¹^ORCID,Chen Yong¹^ORCID,Mak Pui-In¹^ORCID,Martins Rui P.¹^ORCID

Affiliation:

1. State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macau, China

Funder

Science and Technology Development Fund, Macau, SAR

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10083009/09997103.pdf?arnumber=9997103

Reference17 articles.

1. A Closed-Form Transfer Function for Sample and Hold Master Slave Sampling Filter

2. A 25.4-to-29.5GHz 10.2mW isolated sub-sampling PLL achieving ?252.9dB jitter-power FoM and ?63dBc reference spur;yang;IEEE Int Solid-State Circuits Conf Dig Tech Papers,2019

3. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

4. A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 6-GHz 78-fs_RMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM;IEEE Microwave and Wireless Technology Letters;2024-05

2. A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop;AEU - International Journal of Electronics and Communications;2024-04

3. Single-Phase SOGI-PLLs for Fast and Accurate Frequency Ramp Tracking;IEEE Sensors Letters;2023-11