Area Efficient Compression for Floating-Point Feature Maps in Convolutional Neural Network Accelerators
Author:
Affiliation:
1. Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
Funder
Ministry of Science and Technology, Republic of China through Project “Low Power Deep Learning FPGA System for Object Recognition”
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/10032206/09916287.pdf?arnumber=9916287
Reference22 articles.
1. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
2. A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA
3. Cnvlutin
4. SCNN
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