Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects-Reference-Cited by-同舟云学术

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Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects

Published:2022-05-28 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Govindaswamy Prema Kumar¹,Wary Nijwm²,Pasupureddi Vijaya Sankara Rao²

Affiliation:

1. University of Hyderabad,Centre for Advanced Studies in Electronics Science and Technology,Hyderabad,India

2. School of Electrical Sciences, Indian Institute of Technology,Bhubaneswar,Odisha,India

Funder

University Grants Commission

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937255.pdf?arnumber=9937255

Reference9 articles.

1. Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects

2. An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer

3. 5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking

4. An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

5. A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-$\mu{\hbox {m}}$ CMOS

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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