Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology
Author:
Affiliation:
1. Hong Kong University of Science and Technology Clear Water Bay,Department of Electronic and Computer Engineering,Kowloon,Hong Kong
2. Norwegian University of Science and Technology,Department of Electronic Systems,Trondheim,Norway,7034
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937851.pdf?arnumber=9937851
Reference9 articles.
1. FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations
2. Considerations for Ultimate CMOS Scaling
3. Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
4. 5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets
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