Fault Tolerance Evaluation of Different Majority Voter Designs-Reference-Cited by-同舟云学术

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Fault Tolerance Evaluation of Different Majority Voter Designs

Published:2022-05-28 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Oliveira Ingrid F. V.¹,Pontes Matheus F.¹,Schvittz Rafael B.²,Rosa Leomar S.¹,Butzen Paulo F.³,Soares Rafael I.¹

Affiliation:

1. Federal University of Pelotas (UFPel),Technology Development Center,Pelotas,Brazil

2. Federal University of Rio Grande (FURG),Center of Computational Science,Rio Grande,Brazil

3. Federal University of Rio Grande do Sul (UFRGS),Department of Electrical Engineering,Porto Alegre,Brazil

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09938002.pdf?arnumber=9938002

Reference24 articles.

1. Using TMR Architectures for Yield Improvement

2. A simple fault-tolerant digital voter circuit in TMR nanoarchitectures

3. Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

4. Single event transient sensitivity analysis of different 32 nm CMOS majority voters designs

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems;Journal of Electronic Testing;2023-06-20

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