An input folding high speed cyclic ADC for column-parallel readout in CMOS image sensors
Author:
Affiliation:
1. IIT Jodhpur,Department of Electrical Engineering,India
2. IIT Delhi,Department of Electrical Engineering,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937720.pdf?arnumber=9937720
Reference18 articles.
1. An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors
2. A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors
3. A 12 bit, 2-MS/s, 0.016-mm2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator
4. 6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters
5. Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor;Microelectronics Journal;2024-08
2. On Edge FPN Reduction in CMOS Image Sensor Using CNN with Attention Mechanism;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19
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