Look Ahead CLS in Pipelined SAR ADCs
Author:
Affiliation:
1. University of Florida,Department of Electrical and Computer Engineering,Gainesville,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937476.pdf?arnumber=9937476
Reference8 articles.
1. A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping
2. A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS
3. Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp
4. An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain
5. A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
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