A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping

Author:

Hsu Chen-Kai,Sun Nan

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Methods to Improve Linearity of Signal’s Analog-to-Digital Conversion with Self-Calibration;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

2. A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-12

3. Look Ahead CLS in Pipelined SAR ADCs;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

4. A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping;IEEE Journal of Solid-State Circuits;2021-03

5. OTA-Free 1-1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC;IEEE Journal of Solid-State Circuits;2021

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