A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration
Author:
Affiliation:
1. Fudan University,State Key Laboratory of ASIC and System,Shanghai,China,201203
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937746.pdf?arnumber=9937746
Reference13 articles.
1. A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
2. A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks
3. An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier;tang;IEEE Journal of Solid-State Circuits,2020
4. A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier
5. A 0.8–1.2 V 10–50 MS/s 13-bit Subranging Pipelined-SAR ADC Using a Temperature-Insensitive Time-Based Amplifier
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