A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET-Reference-Cited by-同舟云学术

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A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET

Published:2022-05-28 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Lu Ping¹,Boecker Charlie¹,Pandita Bupesh¹,Chen Minhan¹,Nayak Sheethal¹

Affiliation:

1. Silicon Development-SVC, Microsoft Corporation 1009 think place,Morrisville,NC,27560

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937248.pdf?arnumber=9937248

Reference10 articles.

1. A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

2. A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and -256.4-dB FoM

3. A 7.4-to-14GHz PLL with 54fsrms Jitter in 16nm FinFET for Integrated RF-Data-Converter SoCs;turker;IEEE ISSCC Dig Tech Papers,2018

4. A filtering technique to lower LC oscillator phase noise

5. Noise analysis for switched-capacitor circuitry;gai,2008

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