A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking-Reference-Cited by-同舟云学术

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A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

Published:2006-08 Issue:8 Volume:41 Page:1894-1907
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Loke A.L.S.,Barnes R.K.,Wee T.T.,Oshima M.M.,Moore C.E.,Kennedy R.R.,Gilsdorf M.J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/34772/01661764.pdf?arnumber=1661764

Cited by 40 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low TC_L, High-Q Inductors in Standard CMOS;IEEE Microwave and Wireless Technology Letters;2023

2. A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

3. An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications;Microelectronics Journal;2021-11

4. A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process;2020 11th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON);2020-10-28

5. A 0.35-V 240-μW Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications;IEEE Transactions on Biomedical Circuits and Systems;2019-12

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