Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing
Author:
Affiliation:
1. The University of Tokyo,Dept. of Electrical Engineering and Information Systems,Japan
Funder
Technology Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937947.pdf?arnumber=9937947
Reference22 articles.
1. Small Array Area, Memory Error Tolerant ReRAM Computation-in-Memory with Logencoding Simulated Annealing for Combinational Optimization Problems;misawa;Ext Abst of Int Conf Solid State Devices and Mater (SSDM),2021
2. A New Era of Tailored Computing
3. Highly-reliable TaOx reram technology using automatic forming circuit
4. Ising formulations of many NP problems
5. Maximum Cut Problem, MAX-CUT;commander;Encyclopedia of Optimization,2009
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1. Ferroelectric compute-in-memory annealer for combinatorial optimization problems;Nature Communications;2024-03-18
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