A failure analysis framework of ReRAM In-Memory Logic operations
Author:
Affiliation:
1. Institut für Werkstoffe der Elektrotechnik II RWTH Aachen,Aachen,Germany
2. KIT,Department of Computer Science,Karlsruhe,Germany
3. Peter Grünberg Institut (PGI-7) Forschungszentrum Jülich,Jülich,Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9946294/9946242/09946317.pdf?arnumber=9946317
Reference22 articles.
1. Computing in Memory With Spin-Transfer Torque Magnetic RAM
2. Non-Monte-Carlo methodology for high-sigma simulations of circuits under workload-dependent BTI degradation—Application to 6T SRAM
3. Bayesian Optimized Importance Sampling for High Sigma Failure Rate Estimation
4. Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics
5. Unsafe Writing Impacts on the Stateful Memristor Gates
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