A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction-Reference-Cited by-同舟云学术

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A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction

Published:2020-11-09 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Yun Jaekwang,Lee Sangyoon,Jeong Yong-Un,Jeong Shin-Hyun,Kim Suhwan

Funder

Seoul National University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9336024/9336095/09336144.pdf?arnumber=9336144

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

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