Special Session: STT-MRAMs: Technology, Design and Test-Reference-Cited by-同舟云学术

Special Session: STT-MRAMs: Technology, Design and Test

Published:2022-04-25 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 40th VLSI Test Symposium (VTS)
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Author:

Gebregiorgis Anteneh¹,Wu Lizhou¹,Munch Christopher²,Rao Siddharth³,Tahoori Mehdi B.²,Hamdioui Said¹

Affiliation:

1. Delft University of Technology,Department of Quantum and Computer Engineering,Delft,Netherlands

2. Karlsruhe Institute of Technology,Chair of Dependable Nano Computing,Karlsruhe,Germany

3. IMEC,Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9793839/9794139/09794278.pdf?arnumber=9794278

Reference44 articles.

1. Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

2. A 14.7Mb/mm2 28nm FDSOI STT-MRAM with Current Starved Read Path, 52/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference;boujamaa;Symposium on VLSI Circuits,2020

3. Reliability and performance evaluation for STT-MRAM under temperature variation

4. Rare-Failure Oriented STT-MRAM Technology Optimization

5. Novel oxygen showering process (OSP) for extreme damage suppression of sub-20nm high density p-MTJ array without IBE treatment

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1. Advanced Modeling and Simulation of Multilayer Spin–Transfer Torque Magnetoresistive Random Access Memory with Interface Exchange Coupling;Micromachines;2024-04-26

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3. An Overview of Computation-in-Memory (CIM) Architectures;Design and Applications of Emerging Computer Systems;2023-08-17