Custom analog low power design: the problem of low voltage and mismatch-Reference-Cited by-同舟云学术

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Custom analog low power design: the problem of low voltage and mismatch

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Container-title:Proceedings of CICC 97 - Custom Integrated Circuits Conference
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Author:

Steyaert M.,Peluso V.,Bastos J.,Kinget P.,Sansen W.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx3/4814/13308/00606631.pdf?arnumber=606631

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET;Microelectronics Journal;2016-09

2. DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout;ACM Transactions on Design Automation of Electronic Systems;2016-07-26

3. Procesamiento analógico a partir de elementos altamente resistivos;Computación y Sistemas;2013-12-15

4. Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage;Microelectronics Journal;2011-05

5. Containing the Nanometer “Pandora-Box”: Cross-Layer Design Techniques for Variation Aware Low Power Systems;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2011-03

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