Design and Implementation of a 32-bit ISA RISC-V Processor Core using Virtex-7 and Virtex- UltraScale-Reference-Cited by-同舟云学术

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Design and Implementation of a 32-bit ISA RISC-V Processor Core using Virtex-7 and Virtex- UltraScale

Published:2020-10-30 Issue: Volume: Page:
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Container-title:2020 IEEE 5th International Conference on Computing Communication and Automation (ICCCA)
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Author:

Singh Aslesa,Franklin Neil,Gaur Nidhi,Bhulania Paursuh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9250743/9250710/09250850.pdf?arnumber=9250850

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of High Reliability Debugging System for RISC- V Microprocessor;2023 3rd International Conference on Electrical Engineering and Control Science (IC2ECS);2023-12-29

2. Implementing Bit Manipulation Instructions on Architecture of RISC-V Processor;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01

3. A five-stage pipeline processor using the risc-v instruction set architecture designed by system verilog;International Conference on Electronic Information Technology (EIT 2022);2022-05-23

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