A five-stage pipeline processor using the risc-v instruction set architecture designed by system verilog-Reference-Cited by-同舟云学术

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A five-stage pipeline processor using the risc-v instruction set architecture designed by system verilog

Published:2022-05-23 Issue: Volume: Page:
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Container-title:International Conference on Electronic Information Technology (EIT 2022)
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Author:

Qi Shuo,Jin Shaopeng,Xu Yihu,Dai Yilin

Publisher

SPIE

Reference9 articles.

1. Design and Verification Environment for RISC-V Processor Cores;Oleksiak,2019

2. Design and Implementation of a 32-bit ISA RISC-V Processor Core using Virtex-7 and Virtex-UltraScale;Singh,2020

3. A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller;Morales,2019

4. Single cycle RISC-V micro architecture processor and its FPGA prototype;Dennis,2017

5. Siwa: a RISC-V RV32I based Micro-Controller for Implantable Medical Applications;Garcia-Ramirez,2020

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implanting Machine Learning Accelerator with Multi-Streaming Single Instruction Multiple Data Mechanism to RISC-V Processor;2024 IEEE 4th International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB);2024-04-19

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