High-Speed Counter with Novel LFSR State Extension

Author:

Bae Hyungjoon1ORCID,Hyun Yujin1ORCID,Kim Suchang1ORCID,Park Sangsoo1ORCID,Lee Jaeyoung1ORCID,Jang Boseon1ORCID,Choi Suyoung2,Park In-Cheol1ORCID

Affiliation:

1. Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Rep. of KOREA

2. SK hynix Inc, Icheon-si, Gyeonggi-do, Rep. of KOREA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. 64-Bit High Speed Counter with Galois LFSR;2024 International Conference on Circuit, Systems and Communication (ICCSC);2024-06-28

2. Adaptive Reconfigurable LFSR: Dynamic Tapping and Reseeding for Enhanced Pseudo Random Number Generation;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

3. New Programmable LFSR Counters with Automatic Encoding and State Extension;Electronics;2024-01-18

4. CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

5. Advancements in Binary Number Processing: Analyzing a CNTFET-Based Digital Circuit for 3-Bit Up and Down Counting with Challenges in Artificial Intelligence;2023 International Conference on Sustainable Communication Networks and Application (ICSCNA);2023-11-15

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