Optimizing Inter-Core Communications Under the LET Paradigm using DMA Engines

Author:

Pazzaglia Paolo1ORCID,Casini Daniel2ORCID,Biondi Alessandro2ORCID,Natale Marco Di2ORCID

Affiliation:

1. Department of Computer Science, Saarland University, Saarbrücken, Germany

2. Department of Excellence in Robotics and Artificial Intelligence, Real-Time Systems Laboratory (ReTiS Lab), Scuola Superiore Sant’Anna, Pisa, Italy

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Reference38 articles.

1. Addressing analysis and partitioning issues for the Waters 2019 challenge;casini;Proc 10th Int Workshop Anal Tools Methodol Embedded Real-time Syst,2019

2. Implementing time-predictable load and store operations

3. Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures

4. Memory Resource Management for Real-Time Systems

5. Hiding communication delays in contention-free execution for SPM-based multi-core architectures;rouxel;Proc Euromicro Conf Real-Time Syst,2019

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