Optimizing Logical Execution Time Model for Both Determinism and Low Latency-Reference-Cited by-同舟云学术

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Optimizing Logical Execution Time Model for Both Determinism and Low Latency

Published:2024-05-13 Issue: Volume:8 Page:135-148
ISSN:
Container-title:2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)
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Author:

Wang Sen¹,Li Dong¹,Sifat Ashrarul H.¹,Huang Shao-Yu²,Deng Xuanliang¹,Jung Changhee²,Williams Ryan¹,Zeng Haibo¹

Affiliation:

1. Virginia Tech

2. Purdue University

Funder

NSF

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10566868/10568032/10568041.pdf?arnumber=10568041

Reference50 articles.

1. Giotto: a time-triggered language for embedded programming

2. Comparing Communication Paradigms in Cause-Effect Chains

3. Commu-nication centric design in complex automotive embedded systems;Hamann;Euromicro Conference on Real-Time Systems,2017

4. Optimizing Inter-Core Communications Under the LET Paradigm using DMA Engines

5. Optimal Memory Allocation and Scheduling for DMA Data Transfers under the LET Paradigm

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Logical Execution Time and Time-Division Multiple Access in Multicore Embedded Systems: A Case Study;Algorithms;2024-07-05

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