Low-Power and High Speed SRAM for Ultra Low Power Applications
Author:
Affiliation:
1. IIIT Naya Raipur,Dept. of ECE,Naya Raipur,India
2. Jamia Millia Islamia,Dept. of ECE,Delhi,India
3. IIIT Naya Raipur,Dept. of ECE,Raipur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9795657/9795699/09795749.pdf?arnumber=9795749
Reference26 articles.
1. Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes
2. Statistical analysis of low-power SRAM cell structure
3. A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate
4. Cell Stability Analysis of Conventional 6T Dynamic 8T SRAM Cell in 45NM Technology
5. NC-SRAM - a low-leakage memory circuit for ultra deep submicron designs
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1. Ultra-Low Power 9T FinFET Based SRAM Cell for IoT Applications;Journal of Electrical Systems;2024-04-24
2. Comparative Study on 45nm, 90nm and 180nm 6T SRAM Technologies;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23
3. Performance Evaluation of 9T and 6T SRAM Cells at 7nm Technology;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
4. A Review of Low-Power Static Random Access Memory (SRAM) Designs;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07
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