MOSFETs in the VeSTIC process - fabrication and characterization-Reference-Cited by-同舟云学术

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MOSFETs in the VeSTIC process - fabrication and characterization

Published:2017-04 Issue: Volume: Page:
ISSN:
Container-title:2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
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Author:

Tomaszewski Daniel,Domanski Krzysztof,Gluszko Grzegorz,Sierakowski Andrzej,Szmigiel Dariusz

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7954854/7962554/07962604.pdf?arnumber=7962604

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology;2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES);2024-06-27

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