Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology
Author:
Affiliation:
1. Institute of Microelectronics and Optoelectronics, Warsaw University of Technology,Warsaw,Poland
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10613861/10613931/10614028.pdf?arnumber=10614028
Reference14 articles.
1. Integrated circuit device, system, and method of fabrication;Maly;UNITED STATES PATENT,2012
2. Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration;Maly,2011
3. MOSFETs in the VeSTIC process - fabrication and characterization
4. A compact model of VES-BJT device;Kuzmicz,2013
5. Small signal performance of VES-BJT
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