From double to triple gate: Modeling junctionless nanowire transistors-Reference-Cited by-同舟云学术

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From double to triple gate: Modeling junctionless nanowire transistors

Published:2015-01 Issue: Volume: Page:
ISSN:
Container-title:EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
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Author:

Paz Bruna Cardoso,Pavanello Marcelo Antonio,Casse Mikael,Barraud Sylvain,Reimbold Gilles,Faynot Olivier,Avila-Herrera Fernando,Cerdeira Antonio

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7051379/7063712/07063759.pdf?arnumber=7063759

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The role of process and geometrical parameters of gate stack Inverted-T shape junction less FET at 20 nm technology node;Micro and Nanostructures;2024-09

2. DESIGN AND ANALYSIS OF ELECTRICAL CHARACTERISTICS OF INVERTED-T JUNCTIONLESS (JL) FET THROUGH GEOMETRIC AND PROCESS VARIATIONS FOR HIGH FREQUENCY APPLICATIONS;Suranaree Journal of Science and Technology;2024-02-21

3. Doping-less MultiGate Inverted-T shape FET device with Schottky source/drain contacts;Microelectronics Journal;2024-01

4. Radio Frequency Stability Performance of SELBOX Inverted-T Junctionless FET;Multigate Transistors for High Frequency Applications;2023

5. Impact of Device Geometrical Parameter Variation on RF Stability of SELBOX Inverted-T Junctionless FINFET;Silicon;2020-07-29

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