The Study of Bit Line to Storage Node Contact Leakage in Advanced DRAM
Author:
Affiliation:
1. ChangXin Memory Technologies, Inc,Hefei,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9823394/9823964/09825242.pdf?arnumber=9825242
Reference6 articles.
1. New Method for Reduction of the Capacitor Leakage Failure Rate Without Changing the Capacitor Structure or Materials in DRAM Mass Production
2. Trap-Assisted Passing Word Line Leakage and Variable Retention Time in DRAM
3. Analysis of Gate Dielectric Stacks Using the Transmitting Boundary Method
4. Leakage Current in DRAM Memory Cell
5. Technology Scaling Challenge and Future Prospects of DRAM and NAND Flash Memory
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