Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits-Reference-Cited by-同舟云学术

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Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits

Published:2023-12-18 Issue: Volume: Page:160-165
ISSN:
Container-title:2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
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Author:

Zhang Yiran¹,Wang Bo¹,Chen Jinwu¹,Chen Xi¹,Si Xin¹

Affiliation:

1. National ASIC Center Southeast University,Nanjing,China

Funder

National Natural Science Foundation of China

Fundamental Research Funds for the Central Universities

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10387741/10387791/10387923.pdf?arnumber=10387923

Reference20 articles.

1. Efficient Processing of Deep Neural Networks: A Tutorial and Survey

2. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

3. An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width

4. A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs

5. A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update

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