A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET-Reference-Cited by-同舟云学术

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A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET

Published:2023-01 Issue: Volume: Page:
ISSN:
Container-title:2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)
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Author:

Thota Pranay Kumar¹,Rapina Siva Kumar¹,Nistala Bheema Rao²

Affiliation:

1. Mixed Signal Development Group, Microchip Technology India Pvt. Ltd,Bangalore,India

2. National Institute of Technology,Department of ECE,Warangal,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10089791/10089793/10089943.pdf?arnumber=10089943

Reference10 articles.

1. A 10-Gb/s equalizer with digital adaptation

2. A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

3. A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 $\mu\text{s}$

4. The design of continuous-time linear equalizers using model order reduction techniques

5. EQUALIZERS FOR HIGH-SPEED SERIAL LINKS

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 16 Gb/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS;Microelectronics Journal;2024-06

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