Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology
Author:
Affiliation:
1. Indian Institute of Technology,Department of Electrical Engineering,Kanpur,India,208016
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9700979/9700995/09701017.pdf?arnumber=9701017
Reference16 articles.
1. CMOS
2. On-Chip Compensation of Ring VCO Oscillation Frequency Changes Due to Supply Noise and Process Variation
3. Phase Noise and Jitter in CMOS Ring Oscillators
4. Jitter and phase noise in ring oscillators
5. A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator
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1. Comparative Analysis of Phase/Frequency Detector in a Complete PLL System;2023 International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2023-04-29
2. Power Optimal Phase Locked Loop Using 90nm Technology with Five Stage CS-VCO;2022 3rd International Conference on Communication, Computing and Industry 4.0 (C2I4);2022-12-15
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