Author:
Preud'homme Thomas,Sopena Julien,Thomas Gael,Folliot Bertil
Cited by
7 articles.
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1. DRAMHiT: A Hash Table Architected for the Speed of DRAM;Proceedings of the Eighteenth European Conference on Computer Systems;2023-05-08
2. EQueue: Elastic Lock-Free FIFO Queue for Core-to-Core Communication on Multi-Core Processors;IEEE Access;2020
3. Cache‐aware design of general‐purpose Single‐Producer–Single‐Consumer queues;Software: Practice and Experience;2018-12-26
4. A Flexible Communication Mechanism for Pipeline Parallelism;2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC);2017-12
5. An Improvement of OpenMP Pipeline Parallelism with the BatchQueue Algorithm;2012 IEEE 18th International Conference on Parallel and Distributed Systems;2012-12