DRAMHiT: A Hash Table Architected for the Speed of DRAM

Author:

Narayanan Vikram1ORCID,Detweiler David2ORCID,Huang Tianjiao2ORCID,Burtsev Anton3ORCID

Affiliation:

1. University of Utah, Salt Lake City, United States of America

2. University of California, Irvine, USA

3. University of Utah, Salt Lake City, USA

Funder

National Science Foundation

Publisher

ACM

Reference68 articles.

1. Pham Nguyen Quang Anh , Rui Fan , and Yonggang Wen. Balanced Hashing and Efficient GPU Sparse General Matrix-Matrix Multiplication. In Proceedings of the 2016 International Conference on Supercomputing (ICS '16) , 2016 . Pham Nguyen Quang Anh, Rui Fan, and Yonggang Wen. Balanced Hashing and Efficient GPU Sparse General Matrix-Matrix Multiplication. In Proceedings of the 2016 International Conference on Supercomputing (ICS '16), 2016.

2. Main-memory hash joins on multi-core CPUs: Tuning to the underlying hardware

3. Design and evaluation of main memory hash join algorithms for multi-core CPUs

4. Silas Boyd-Wickizer , M Frans Kaashoek , Robert Morris , and Nickolai Zeldovich . Non-scalable locks are dangerous . In Proceedings of the Linux Symposium , pages 119 -- 130 , 2012 . Silas Boyd-Wickizer, M Frans Kaashoek, Robert Morris, and Nickolai Zeldovich. Non-scalable locks are dangerous. In Proceedings of the Linux Symposium, pages 119--130, 2012.

5. Intel Corporporation. Intel® Memory Latency Checker. https://www.intel.com/content/www/us/en/developer/articles/tool/intelr-memory-latency-checker.html. Accessed: 2022-05-18. Intel Corporporation. Intel ® Memory Latency Checker. https://www.intel.com/content/www/us/en/developer/articles/tool/intelr-memory-latency-checker.html. Accessed: 2022-05-18.

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1. DLHT: A Non-blocking Resizable Hashtable with Fast Deletes and Memory-awareness;Proceedings of the 33rd International Symposium on High-Performance Parallel and Distributed Computing;2024-06-03

2. CoroGraph: Bridging Cache Efficiency and Work Efficiency for Graph Algorithm Execution;Proceedings of the VLDB Endowment;2023-12

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